AXI4-to-axi3 converter

The AXI4-to-AXI3 converter is a VHDL IP developed by Truestream. It adapts AXI4 transactions to be compliant with the older version of the standard. It is designed to have a very small logic footprint while maintaining full throughput. See the product sheet for details.

Please contact info@truestream.se for more information and a quote.

AXI CROSSBAR

The AXI crossbar is a VHDL IP developed by Truestream. It performs N-to-1 arbitration of AXI buses. It is designed to have a very small logic footprint while maintaining full throughput. See the product sheet for details.

Please contact info@truestream.se for more information and a quote.

AXI DATA WIDTH CONVERTER

The AXI data width converter is a VHDL IP developed by Truestream. It can be used for upconversion and downconversion of AXI read/write transactions. The IP is designed to be very resource efficient but still achieve high performance. See the product sheet for details.

Please contact info@truestream.se for more information and a quote.

AXI interconnect

The AXI interconnect is a VHDL IP developed by Truestream. It is used to connect many AXI masters, that might be of different widths and in different clock domains, to a single physical AXI port. It guarantees 100% throughput in all scenarios with no clock cycles wasted.

Please contact info@truestream.se for more information and a quote.

AXI MASTER

The AXI master, also known as a "data mover" or "AXI MM2S/S2MM", is a VHDL IP developed by Truestream. It provides a simple memory read/write interface that hides the complexity of raw AXI transactions. This IP by Truestream guarantees full bus utilization and yet has a very small logic footprint.

Please contact info@truestream.se for more information and a quote.

SLOW FIR FILTER

The slow FIR filter is a VHDL IP developed by Truestream. It is designed to be used in signal processing when the data sample rate is significantly lower than the clock frequency. It uses only a single DSP element and minimal LUT/FF compared to competitors. See the product sheet for details.

Please contact info@truestream.se for more information and a quote.

tsfpga

The open source project tsfpga, a development platform that aims to streamline all aspects of your FPGA project, is authored and maintained by Truestream employees. It provides a python build/simulation flow, along with complementary VHDL components, that is perfect for CI/CD and test-driven development. Focus has been placed on flexibility and modularization, achieving scalability even in very large multi-vendor code bases.

Note that tsfpga is not a commercial interest of ours. It is run completely as an open source community project. There are no paid premiums and no strings attached. It is released under the permissive BSD 3-Clause License. You are welcome to clone, modify, and submit patches at the gitlab page: https://gitlab.com/tsfpga/tsfpga

Complete documentation is available on the website: https://tsfpga.com