Our IPs offer the following benefits:
- Very low resource utilization.
- Portability thanks to human-readable source code.
- Flexibility thanks to extensive user parametrization.
- Good tests, with testbenches included in delivery.
- Proper and up-to-date documentation.
Using IPs with these qualities will significantly improve your time to market. If you want any other IP to be designed with these qualities, please contact us for a discussion.
AXI4-TO-AXI3 CONVERTER
The AXI4-to-AXI3 converter adapts AXI4 transactions to be compliant with the older version of the standard. It is designed to have a very small logic footprint while maintaining full throughput. See the documents below for more details.
AXI4-to-AXI3 converter product sheet (PDF)
AXI4-to-AXI3 converter documentation (HTML)
AXI CROSSBAR
The AXI crossbar performs N-to-1 arbitration of AXI buses. It is designed to have a very small logic footprint while maintaining full throughput. See the documents below for more details.
AXI crossbar product sheet (PDF)
AXI crossbar documentation (HTML)
AXI DATA WIDTH CONVERTER
The AXI data width converter can be used for upconversion and downconversion of AXI read/write transactions. The IP is designed to be very resource efficient but still achieve high performance. See the documents below for more details.
AXI data width converter product sheet (PDF)
AXI data width converter documentation (HTML)
AXI INTERCONNECT
The AXI interconnect is used to connect many AXI masters, which may be of different widths and in different clock domains, to a single physical AXI port. It guarantees 100% throughput in all scenarios with no clock cycles wasted. See the documents below for more details.
AXI interconnect product sheet (PDF)
AXI interconnect documentation (HTML)
AXI MASTER
The AXI master, also known as a “data mover” or “AXI MM2S/S2MM”, provides a simple memory read/write interface that hides the complexity of raw AXI transactions. This Truestream IP guarantees full bus utilization while having a very small logic footprint. See the documents below for more details.
AXI master product sheet (PDF)
AXI master documentation (HTML)
OFF-CHIP FIFO
The off-chip FIFO implements a FIFO structure that stores data in DDR SDRAM, unlike traditional FIFOs that use Block RAM or LUTRAM. The IP has unique versatility and user configurability while maintaining a very small logic footprint. See the documents below for more details.
Off-chip FIFO product sheet (PDF)
Off-chip FIFO documentation (HTML)
SLOW FIR FILTER
The slow FIR filter is designed for signal processing when the data sample rate is significantly lower than the clock frequency. It uses only a single DSP element and minimal LUT/FF compared to competitors. See the documents below for more details.
Slow FIR filter product sheet (PDF)
Slow FIR filter documentation (HTML)